High speed, low power input buffer
US5039881A · kind A · utility
4Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1989 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Jun 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer includes an input circuit (80), a pair of complimentary outputs (52,54) and a differential ampliifer (12). The input buffer includes a pull-down diode (90) arranged in parallel with pull-up diodes (84, 86, and 88), coupled between the buffer input (82) and the differential amplifier input (32). Pull-up is achieved through the low impedance path of the pull-up diodes, eliminating a need for a high value resistor. Pull-down is achieved through the pull-down diode in series with a resistor (92). This arrangement provides high speed of operation, while reducing current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.