Address decoder circuit for non-volatile memory
US5039882A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1989 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Oct 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate portion comprising a load MOS transistor and an address input MOS transistor is rendered different from that during a writing or reading operation, and a third potential is applied to the power terminal proximate to the address input MOS transistor and also to the power terminal of a buffer, whereby the third potential is outputted to prevent erasure in the state of non-selection. The resistance of load means is changed to be greater in a writing operation for reducing the power consumption during the writing operation and minimizing the dimensions of component elements. And in a voltage supply circuit, for the purpose of outputting a desired voltage without providing any additional circuit which may consume great power or without causing any level reduction of a first or write voltage, a MOS transistor for outputting the first voltage is controlled in response to a signal obtained by boosting the volt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.