Integrated semiconductor device including an insulated-gate field effect transistor biased to a constant level in order to produce a negative differential drain conductance zone
US5039958A · kind A · utility
4Cited by
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17Claims
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Key dates
| Filing date | Jan 19, 1990 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Jan 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor device, including an insulated-gate field effect transistor biased to a constant level in order to obtain for the transistor an N-shaped drain-source current characteristic as a function of the drain-source voltage so that it presents a negative differential conductance zone, characterized in that it comprises means for applying, between the drain and the source of the field effect transistor, a voltage whose value is in the range of values the drain-source voltage corresponding to the negative conductance zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.