Self-aligned, high resolution resonant dielectric lithography
US5040020A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1989 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Nov 2, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D44/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating electrical contacts on both sides of a thin membrane to form a millimeter wave, self-aligned, opposed gate-source transistor are disclosed. The transistor structure has a subhalf-micron gate, dual-drains placed symmetrically around both sides of the gate, and a source approximately half the length of the gate. The source is directly opposite, and centered under, the gate on the opposite surface of a semiconductor thin film. The gate electrode is fabricated on the first surface of the thin film using conventional single surface lithography, and is used as a conformed mask for the source lithography, thereby self-aligning the source to the gate. The source is formed by resonant dielectric lithography, wherein the gate side of the thin film is irradiated by collimated ultraviolet light to expose a negative resist on the source side with a resolution of less than a wavelength. Lateral diffraction effects affect the relative dimension of the source with respect to the gate. The electron-beam lithographic process utilizes electron scattering in the thin film for the same purpose. This new untraviolet lithography process avoids the need to handle the thin film until…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.