Hybrid circuit comprising a cascade connection of parallel-transistor stages
US5040050A · kind A · utility
1Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1990 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Oct 11, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This circuit is such that the semiconductor chips constituting the various transistors of the circuit are organized in a matrix in which the various columns are formed on a first network of conductor tracks and are separated by second and third networks of conductor tracks, said networks being connected to respective different connection tabs of the semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.