Circuit for simultaneous arithmetic calculation and normalization estimation
US5040138A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 1989 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Aug 2, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) performs a three-bit overlapping scan of the signed digit differene to determine a bit location which corresponds to the approximate bit position of the most significant non-zero bit in the result of the arithmetic process performed in adder/rounder circuit (20). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue. The number of leading zeroes is output to a barrel shifter (16) via an L-bus (30). The operands are simultaneously substracted in adder/rounder circuit (20) and the result is input into barrel shifter (16) via an M-bus (12). The result is then shifted in barrel shifter (16) according to the leading zero count input by leading zero coun…
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