Semiconductor memory device
US5040143A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1990 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | May 22, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second supply lines are connected to some or all of a plurality of memory cells included in a memory cell array. Only the first supply line is connected to the remaining memory cells. When a voltage of H level is supplied to the first and second supply lines, all memory cells function as SRAM memory cells in which stored information can be rewritten. Meanwhile when H level is applied to the first supply line and L level is applied to the second supply lines, memory cells to which both the first and second supply lines are connected are set to a state in which information of the logic "1" or "0" is fixedly stored. Namely, they function as ROM memory cells. At this time, the remaining member cells to which only the first supply line is connected function as SRAM memory cells. In this manner, by switching the voltages applied to the second supply line, some or all of the memory cell arrays function as SRAM or ROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.