High data rate BCH encoder
US5040179A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1989 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Aug 18, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An encoder for selected linear error correcting codes, such as a BCH code, uses relatively low-speed circuitry to generate parities for correcting the code. A parity matrix derived from the BCH generator matrix is provided as data to a generator vector whereby the generator vector is used as a logical shift function generator. When the logical shift function is applied to the rows of the parity matrix, columns of parity are shifted into an EXCLUSIVE-OR tree to produce the parity bit of the column. The parity bit of the column is then injected into a data stream forming the encoded symbol for transmission, attaching the parity word following the data word. The apparatus may be constructed making maximum use of the standard, commerically available, relatively low-cost integrated circuits, but it is nevertheless capable of operating at speeds in excess 1 GBPS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.