Timer channel with match recognition features
US5042005A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 19, 1988 |
| Grant date | Aug 20, 1991 |
| Priority date | — |
| Expiry date | Aug 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timer subsystem which provides a data processor servicing the timer subsystem with the ability to inhibit the match recognition logic of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem with a dedicated service processor. The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register, for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.