Digital-to-analog converter having a ladder type resistor network
US5043731A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Aug 14, 1990 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Aug 14, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter includes a ladder type resistor network having stages equal in number to bits of a digital input signal, each of the stages including a first resistor and a second resistor mutually connected in series via a node. A first switch, which is provided for each of the stages, selectively supplies either an upper limit voltage or a lower limit voltage to a corresponding one of the stages in accordance with a logical value of a corresponding one of the bits of the digital input signal. An analog signal output terminal is coupled to the node of one of the stages which corresponds to a most significant bit of the digital input signal. An analog output signal is output via the analog signal output terminal. An offset level control resistor has a first end connected to the node of one of the stages which corresponds to a least significant bit of the digital input signal and a second end. A second switch, which is coupled to the second end of the offset level control resistor, selectively supplies either the upper limit voltage or the lower limit voltage to the second end of the offset level control resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.