Display locked timing signals for video processing
US5043813A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1990 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Mar 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for receiving a video signal with a horizontal synchronizing component at a horizontal scanning frequency generates an intermediate synchronizing signal synchronized with the horizontal synchronizing component. A horizontal deflection circuit generates horizontal deflection current synchronized with the intermediate synchronizing signal. An oscillator generates a display locked clock signal synchronously with a clock synchronizing signal derived from the horizontal deflection current. A counter divides the clock signal, producing decodable outputs. A decoding circuit generates display locked timing signals, at the frequency of the horizontal synchronizing component and at the frequency of the intermediate signal, from the outputs of the counter. Where the frequency of the intermediate signal is a multiple of the frequency of the horizontal synchronizing component, for example by a factor of two, a circuit coupled to the counter and the decoding circuit associates certain pulses of the display locked clock signal with commencement of video line intervals in the video signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.