Exception reporting mechanism for a vector processor
US5043867A · kind A · utility
45Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1988 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Mar 18, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30189
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data process system capable of executing vector instructions and scalar instructions detects the occurrence of arithmetic exception conditions and allows subsequent scalar instruction processing until execution of the next vector instruction is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.