Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
US5043874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-processing computer system including a plurality of central processing units (CPUs) and input/output (I/O) units, a system memory including a plurality of DRAM-based memory segments, a system control unit (SCU) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data therebetween, the system memory is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read data from addressed memory segments to the interface for transfer to the SCU, a second dedicated data path for transfer of write data received from the SCU through the interface to addressed memory segments, and a third dedicated path for transfer of addresses from the SCU to identify addressed segment of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.