Nand cell type programmable read-only memory with common control gate driver circuit
US5043942A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1990 |
| Grant date | Aug 27, 1991 |
| Priority date | — |
| Expiry date | Jun 4, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.