PdIn ohmic contact to GaAs
US5045502A · kind A · utility
33Cited by
3References
14Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 10, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | May 10, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ohmic contact to a semiconductor such as GaAs and its method of making in which a thin layer of Pd is overlaid preferably with a layer of Group-IV element such as Ge followed by another layer of Pd. This structure is then overlaid with a layer of Pd and In. The atomic ratio of the Pd and In in the entire structure lies between 0.9 and 1.5. This structure is then annealed at a temperature between 350.degree. C. and 675.degree. C. There results a very thin crystalline layer of Ge-doped InGaAs adjacent the GaAs and an overlying PdIn alloy layer providing a contact resistance in the range of 0.1-1 .OMEGA.-mm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.