Circuit for generating stretched clock phases on a cycle by cycle basis
US5045715A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Mar 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge coherent with the first clock signal, including the stretched clock phases. The circuit inputs a signal generated by an oscillator which is twice the frequency of the CLK signal which is then used to generate the CLK signal for use by a microprocessor, either phase of which can be stretched on demand, while the second 2X CLK signal remains phase coherent with the microprocessor CLK signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.