Data processor
US5045997A · kind A · utility
71Cited by
6References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1988 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Oct 28, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in the sequential operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.