Multi-function timing sequencer for different speed main storage units
US5045999A · kind A · utility
6Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1989 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Sep 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B19/07
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.