Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory
US5046023A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 6, 1987 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Oct 6, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/399
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphic processing system including a main memory for storing a program and information corresponding to pixels, a main processor for effecting an execution processing of a program transferred from the main memory or from an external device so as to control the system, display/output devices such as a CRT device and a printer for outputting graphic information attained by controlling pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels outputted to the display/output devices, and a graphic processor for receiving a command and parameter information transferred from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or the frame buffer, respectively. The system also includes bus connection switch circuit to be controlled by the graphic processor to effect a connection control between the first and second address buses and between the f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.