Method of flash write for testing a RAM
US5046049A · kind A · utility
11Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1990 |
| Grant date | Sep 3, 1991 |
| Priority date | — |
| Expiry date | Mar 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device(DRAM), an improved flash write test method is disclosed whereby all the memory cells in a memory cell array of a memory device can be written with the internally same data or the externally same data. The bit lines are arranged such that the bit lines B/L and B/L are alternating throughout the memory cell array and such that one word line is connected to only one type(either B/L or B/L) of bit lines, and the data supply circuit is formed by a data controller which controls input/output drives according to the type of the bit lines connected to the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.