Stacked capacitor for semiconductor memory device
US5047817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1989 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Jun 9, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.