Semiconductor integrated circuit device having a decoder portion of complementary misfets employing multi-level conducting layer and a memory cell portion
US5047825A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 27, 1990 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Feb 27, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed. Concretely, the method comprises the steps of providing selector switch elements which serve to select decode signal lines in accordance with address signals received from pairs of complementary address signal lines, each pair including a true line and a bar line, in a decoder forming region of a semiconductor substrate; providing a conductor film which is connected to input terminals of the selector switch elements and which is extended under regions for forming the true lines and the bar lines; providing an interlayer insulator film on the selector switch elements and the conductor film; forming contact holes in the interlayer insulator film on the conductor film so as to reach the conductor film; and connecting either of the true lines and the bar lines to the conductor film…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.