Standard cell LSI layout method
US5047949A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1990 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Jun 6, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.