High density SRAM circuit with ratio independent memory cells
US5047979A · kind A · utility
320Cited by
1References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1990 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Jun 15, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, a high density, static, random access memory (SRAM) circuit with ratio independent memory cells employs a number (plurality) of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells of the present invention differs from corresponding, prior art type SRAM cells in that the SRAM cells of the present invention each include transistors of similar size (channel width).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.