Semiconductor storage device with redundancy arrangement
US5047983A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1990 |
| Grant date | Sep 10, 1991 |
| Priority date | — |
| Expiry date | Sep 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor storage device having a spare memory, an input address signal is checked by an address comparator circuit. When the input address signal indicates an address which is to be relieved, the spare memory is selected instead of a memory array on the basis of the output of the address comparator circuit at that time. In conventional system, the access time of the semiconductor memory is restricted substantially by the operating time of the address comparator circuit during this operation. Accordingly, for enabling a quick access of the semiconductor memory, an address signal to be supplied to the address comparator circuit is output from a proceeding stage circuit of a plurality of amplification stages which form an address buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.