Testing of integrated circuits using clock bursts
US5049814A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1989 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Dec 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.