Multiple sliding register stacks in a computer
US5050067A · kind A · utility
30Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1990 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Feb 27, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register architecture for a computer in which a plurality of banks of general purpose registers are used in the register files. Each of the multiple register banks is dedicated to a different user, with one of the register banks being dedicated to servicing interrupts and another of the register banks being dedicated to the operating system of the computer in which the register architecture is incorporated. Associated with each of the register banks is a smaller register bank of status registers in which information concerning the status of the computer is stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.