Memory device with improved common data line bias arrangement
US5050127A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1989 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Oct 19, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.