Device for synchronizing a clock in relation to an incident digital signal, in particular at high transmission rates
US5050193A · kind A · utility
6Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1988 |
| Grant date | Sep 17, 1991 |
| Priority date | — |
| Expiry date | Nov 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The device comprises preprocessing circuitry which deliver to a phase locked loop a preprocessed signal obtained from a replica of the incident digital signal staggered in time by a fraction of the cycle of the clock signal of the phase locked loop. This device then allows a fast synchronization of the clock of the phase locked loop in relation to the incident digital signal, in particular at high transmission rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.