TTL tristate circuit for output pulldown transistor
US5051623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1990 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Jun 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0826
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver. The emitter follower DCMK signal output and voltage divider coupling reduce DCMK signal generation delay, eliminate current hogging between Miller killer transistor elements of the multiple output buffers of a multi-bit output, and dispense with t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.