Output buffer circuits for reducing noise
US5051625A · kind A · utility
65Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1989 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Oct 27, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit, in which a pair of current sources is connected to positive and negative power sources, and a first inverter having input and output terminals, is arranged between the current sources, in which a second inverter having input and output terminals, is connected to the output terminal of the first inverter, the second inverter including at least one of P-channel and N-channel MOSFETs, and a capacitor is connected between the input and output terminals of the second inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.