Solder or brazing barrier
US5051811A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1989 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Jan 27, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2081
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of preparing a substrate such as a semiconductor chip or ceramic thin film having vias for soldering to a substrate requires that a first metal that is resistive to solder bonding be deposited on the backside of the semiconductor device. The deposited metal is removed from the surface of the semiconductor device, leaving the vias of the semiconductor device having the first metal deposited through them. This technique is useful in any requirement requiring a solder or brazing barrier. This is, a photolithographic process in conjunction with a refractory or nonsolderable metal deposit is used to achieve an alloy or solder barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.