Multi-layer semiconductor device
US5051865A · kind A · utility
66Cited by
9References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 11, 1991 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Mar 11, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer semiconductor device which includes a stacked wafer body having a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween. An end of the heat sink plate of each set of wafers is exposed at at least one of the side surfaces of the stacked wafer body. An intermediate connecting circuit is provided for connecting circuits in each of the sets of two semiconductors wafers, the intermediate connecting circuit is provided on at least one side surface other than the surface at which the ends of the heat sink plate are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.