Apparatus and method for nullifying delayed slot instructions in a pipelined computer system
US5051896A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1988 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Mar 21, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is fetched, the operation specified by the first instruction is performed and the results of the operation are stored, including the state of the nullification field. The second instruction is fetched and the operation specified by the second operation is performed. However, conditional upon the state of the nullification field of the first instruction, results, errors, traps and interrupts of the second instruction are not stored in the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.