Data dependency collapsing hardware apparatus
US5051940A · kind A · utility
68Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1990 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Apr 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.