Semiconductor memory having improved data readout scheme
US5051955A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1990 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Jun 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device capable of reading out stored data at high speed and with low power consumption includes a sense amplifier for amplifying a data signal stored in a selected memory cell, a data latch circuit for latching the output signal of the sense amplifier, a switching circuit for outputting the output signal of the data latch circuit, and an output circuit for receiving the output signal of the sense amplifier and the output signal of the switching circuit and generating a data output signal. It also includes at the power supply side, switching means for keeping the sense amplifier in an operative state as long as data signal is amplified in response to a sense enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.