Phase adjustment circuit
US5051990A · kind A · utility
13Cited by
6References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1990 |
| Grant date | Sep 24, 1991 |
| Priority date | — |
| Expiry date | Jan 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A phase adjustment circuit uses a broad band circuit for processing a plurality of high speed highway data comprising m bit frames. The phase adjustment circuit provides a master frame pulse based on a frame pulse selected from respective frame pulses in the high speed highway and delayed in phase by the maximum amount and provides a master clock based on a high speed highway clock corresponding to the master frame pulse. The phase adjustment circuit receives a plurality of high speed highway data by using the master clock and the master frame pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.