Method and apparatus for high speed phase detection
US5053649A · kind A · utility
13Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1990 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Dec 6, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detector particularly suited for high speed, digital data. The data is auto-correlated with the data shifted through a flip-flop where the flip-flop is clocked by the clocking signal. The data is also delayed by one period by an analog delay line. The output of the flip-flop is auto-correlated with the data and with the data shifted by one period to provide an error signal for a VCO. Ordinary ECL circuits in leaded packages may be employed with data rates in the 300 MHz range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.