Deglitched digital mixer circuit
US5053651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1990 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Aug 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital mixer employs a plurality of flip-flops to mix two digital input signals and provide a beat frequency output. The first input signal is provided as a clock signal to a first D flip-flop and to a third JK flip-flop. The second input signal is provided as a clock signal to a second D flip-flop. The inverted output of the first flip-flop is provided as a clock input to a fourth JK flip-flop. The non-inverted and inverted outputs of the second flip-flop are connected, respectively, to the J and K inputs of the third flip-flop. The non-inverted outputs of the second and third flip-flops are input to a first AND gate, the output of which connects to the J input of the fourth flip-flop. Likewise, the inverted outputs of the second and third flip-flops are input to a second AND gate, the output of which connects to the K input of the fourth flip-flop. The non-inverted output of the fourth flip-flop provides a beat frequency that is one-half the difference frequency of the two input signals. The third flip-flop in the digital mixer prevents glitches around the transition time of the beat frequency output even for very low beat frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.