Nonvolatile semiconductor memory

US5053841A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Tadashi Miyakawa · Yokohama, JP
• Masamichi Asano · Oshima, JP
• Tadayuki Taura · Zushi, JP
• Atsushi Shoji · Kawasaki, JP
• Michiharu Inami · Tama, JP

Key dates

• Filing date: Oct 18, 1989
• Grant date: Oct 1, 1991
• Expiry date: Oct 18, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/686

Abstract

A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to eac…