Apparatus for providing single event upset resistance for semiconductor devices
US5053848A · kind A · utility
21Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1988 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Dec 16, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.