Variable modulus digital synthesizer
US5053982A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1989 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Feb 14, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0335
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synthesizer capable of generating a multiplicity of output frequency signals with 1 hertz resolution utilizing binary mathematics in a binary circuit. The apparatus includes providing to an accumulator a stable reference input signal having a frequency value of K, a defined value of 2.sup.N where N is an integer, a rollover value R equal to 2.sup.N minus the synthesizer modulus M and a desired output frequency signal having a value V selected from the range of integer values between 1 and K. The accumulator, at the rate of K, periodically increments the accumulator contents A by the value V, until the accumulated value exceeds 2.sup.N -1. The accumulator's content A is then set at the next cycle of the reference input signal K to a value of A-2.sup.N +R+V. A convertor converts the values of A into an output signal. In the preferred embodiment, the accumulator includes digital circuitry having 2.sup.N capacity and performs binary arithmetic to accomplish the accumulations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.