Arithmetic unit in a vector signal processor using pipelined computational blocks
US5053987A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1989 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Nov 2, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands. The operands are fetched from an internal data buffer from, for example, sources internal to the integrated circuit such as internal RAM, ROM and arithmetic registers. Computation results from the Multiplier, the Adder, and the Adder-Subtracter are temporary …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.