Dynamic random access memory with FET equalization of bit lines
US5053997A · kind A · utility
20Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1987 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Dec 8, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory with a folded bit line structure (BLL.sub.j1, BLL.sub.j1, BLR.sub.j1 BLR.sub.j1), each pair of bit lines being divided into a plurality of blocks (MCB.sub.j1, MCB.sub.j2), comprises equalizing transistors (Q.sub.j9, Q.sub.j10) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q.sub.j9, Q.sub.j10) stop equalizing selectively and at different times among the blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.