Transistor breakdown protection circuit
US5054001A · kind A · utility
9Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1990 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Apr 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention relates to transistor breakdown protection circuits for use in high voltage circuitry. This inventions relates more particularly to memory systems such as Electrically Erasable Programmable Read Only Memory (EEPROM), or Non-Volatile Random Access Memory (NVRAM) which require high voltages for write and erase operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.