Apparatus for scrambling/descrambling data by word-by-word processing
US5054069A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1990 |
| Grant date | Oct 1, 1991 |
| Priority date | — |
| Expiry date | Aug 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03872
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A scrambling/descrambling apparatus has a data memory for storing a data word, a bit invert flag, and numerical data. A bit shift operating section performs, on receiving a bit of data to be outputted or a bit of input data, a bit shift operation with that bit and stores resultant data in the data memory in the form of a first data word. A randomizing/derandomizing section randomizes or derandomizes the input data by using the first data word and based on a generating polynomial and, depending on a state represented by the bit invert flag, inverts the bit of the data to be outputted to develop output data. A count processing section increments or decrements the numerical value stored in the data memory and, depending on the numerical value, selectively sets the bit invert flag to a predetermined state. A count controlling section replaces the numerical value with a predetermined initial value on the basis of the first data word and bit invert flag. The data memory holds a second and a third data word, bits of which corresponding in position to a particular bit of the first data word are a ZERO and a ONE, respectively. The count controlling section reads selectively either one of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.