Multiaccumulator sigma-delta fractional-N synthesis
US5055802A · kind A · utility
103Cited by
11References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1990 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Apr 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.