Extended integration semiconductor structure with wiring layers
US5055907A · kind A · utility
192Cited by
13References
44Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Jan 25, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.