Analog hardware for learning neural networks
US5056037A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Dec 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This is a recurrent or feedforward analog neural network processor having a multi-level neuron array and a synaptic matrix for storing weighted analog values of synaptic connection strengths which is characterized by temporarily changing one connection strength at a time to determine its effect on system output relative to the desired target. That connection strength is then adjusted based on the effect, whereby the processor is taught the correct response to training examples connection by connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.