Semiconductor memory having error correction circuit
US5056095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 1989 |
| Grant date | Oct 8, 1991 |
| Priority date | — |
| Expiry date | Jan 12, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce the number of wirings required between a plurality of memory blocks and a plurality of error correction circuits and thereby reduce the chip area occupied by a semiconductor memory, the present invention provides a semiconductor memory which comprises (1) a plurality of memory blocks (12) for storing information bits, (2) another memory block (13) for storing test bits, (3) a plurality of multiplexers (26) disposed at the respective output sections of the memory blocks (12), (4) a plurality of parity test circuits (27) each responding to bit information for a parity test which is generated from one output from the corresponding one of the multiplexers (26), (5) a syndrome bus (22) responding to both the respective outputs of the parity test circuits (26) and the output of the another memory block (13), and (6) a plurality of error correction circuits (21) each responding to both output data (28) generated from the other output of the corresponding one of the multiplexers (26) and a syndrome generated from the syndrome bus (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.